Chip carriers, substrates, and passive boards used for electronic component packaging usually include metal interconnections, voltage planes, and dielectric materials such as ceramic, glass ceramic, silicon-oxide, polymer, and/or epoxy glass. An exemplary board used for electronic component packaging is shown in FIG. 1. In this figure, circuit board 5 is a multi-layer circuit board which has not been populated with electrical components. At least one of the layers within circuit board 5 is a power plane 4. Furthermore, at least one other of the layers is a ground plane 6. A plurality of interconnection networks, hereinafter "nets", are also included in circuit board 5. Circuit board 5 is shown including NET 1 and NET 2. Each net may be distributed either across a single layer or across multiple layers within circuit board 5.
As the packaging density in such boards continues to increase, the metal interconnections which make up each net are getting smaller and closer together. This continual miniaturization of the metal interconnections within circuit boards leads to an increase in the probability of a variety of defects. For example, the points of a conductor network which should be connected together may have one (or more) discontinuities in the conductor path(s). This results in an "open circuit" condition with substantially infinite resistance between certain sections of the network. A further defect occurs when two independent conductor networks or conductor areas which are intended to have no electrical connection, and therefore, substantially infinite internet resistance, in fact display an unacceptable, low value of internet resistance. This is commonly referred to as a "short circuit". In addition, a conductive pathway may be defective because it displays one or more sections having resistances which exceed an acceptable level. This defect is referred to as a "resistive fault".
In a properly manufactured high-density passive board, the resistance between terminals of a common conductor network is normally in the range of from a few milliohms to many ohms. This resistance is dependent on the length and cross section of the conductors. Furthermore, the resistance between independent networks should approach infinity. This resistance typically exceeds 100 megohms.
A necessary step in the manufacture of high-density substrates, chip carriers, and passive boards is to test the proper continuity and isolation of all nets before any electronic components are mounted. Continuity testing measures relatively low resistance within particular networks. Open circuits and resistive faults are thus typical defects which are found in continuity testing. Isolation testing measures the expected high resistance levels that should exist between conductors. Short circuits are typical defects which are found in conducting isolation testing.
A common continuity and isolation test method uses cluster probes which match and contact to test pads on the substrate surface. By controlling the switching matrix, resistance from a network under test to all other networks in the substrate can be measured. This is a relatively fast testing method, however, it lacks flexibility. Substrates with different designs usually require different cluster probes or bed-of-nail fixtures. In addition, complexity and long lead-time to produce custom cluster probes makes this technique costly, especially for early manufacturing where product design may not be fixed.
Another isolation test is the so called point-to-point testing wherein two moving probes are used on an X-Y positioning mechanism. This flexible probing method can perform individual tests between all possible pairs of nets. An exemplary "moving probe" mechanism is disclosed in U.S. Pat. No. 4,565,966 (Burr et al.). Burr discloses the testing of passive substrates using moving probes in a series of two-point resistance measurements. In this manner, the continuity of individual nets may be verified. In addition, using this method a series of one-point measurements may be made to determine the capacitance of a network relative to a reference plane or to indicate short-circuits between nets through excessive internet capacitance. While this approach has great flexibility, it suffers from several severe practical difficulties which limit its effectiveness and speed. These include a need for switching between resistance and capacitive test modes, difficulty of detecting a low-capacitance net shorted to a high-capacitance net when testing the high capacitance net, and an inability to distinguish between a high-resistance short to a net and a leakage path directly to ground. Furthermore, this method relies on simple scalar matching of capacitance values during the defect isolation process. In this manner, the continuity of nets which display excessive capacitance is checked against a potentially long list of other nets showing similar capacitance.